A gbit-scale dram stacked capacitor with ECR MOCVD SrTiO3 over RIE patterned RuO2/TiN storage nodes

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Abstract
The capacitor requirements for Gbit-scale DRAMs are discussed in detail. The choice of SrTiO3 thin films over a stacked RuO2/TiN structure for the 1 Gbit DRAM is explained, and particular emphasis is put on the necessity of a stacked capacitor structure and on the selection of a suitable electrode material. The influence of film composition, film thickness and substrate temperature on the properties of ECR MOCVD SrTiO3 films is then presented. Maximum permittivity and low leakage current density were obtained for stoichiometric composition, Sr/Ti = 1·0. A thickness of at least 400 Å was found to be necessary to obtain SrTiO3 films with sufficient electrical properties. A substrate temperature of 450°C was found to be a suitable temperature for direct deposition of crystallized SrTiO3 and no degradation of the RuO2/TiN bottom electrode structure. A new reactive ion etching process was developed to pattern RuO2/TiN nodes. The key characteristics of this process are the use of an SOG mask, the choice of an O2/Cl2 gas mixture which allows reactive etching of RuO2 at a high rate of 2500 Å/min and with a RuO2/SOG selectivity more than 10:1, and an O2 ashing treatment performed at 150°C at the end of the etching process, which helps remove the damaged layer observed at the RuO2 surface after RuO2/TiN etching. A new stacked capacitor technology comprising reactive ion etching of RuO2/TiN storage nodes and low temperature deposition of SrTiO3 thin films by ECR MOCVD at 450°C was successfully developed. A storage capacitance of 25 fF and a leakage current density of 8 × 10−7 A/cm2 can be obtained at half Vcc = + 1·0 V, for SrTiO3 films with a sidewall thickness of 400 Å deposited on 0·5 μm stacked RuO2/TiN storage nodes. This capacitor technology is suitable for use in Gbit-scale DRAMs.