Performance improvement of the memory hierarchy of RISC-systems by application of 3-D-technology

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Abstract
In this paper, potential performance improvements of the memory hierarchy of RISC-systems for implementations employing 3-D-technology are investigated. Relating to RISC-systems, 3-D ICs will offer the opportunity for integrating much more memory on-chip (i.e. on one IC or 3-D IC with the processor). As a result, the second-level cache may be moved on-chip. The available on-chip cache may alternatively be organized in three levels. Investigations were also performed for the case of the main memory being integrated on-chip. Current restrictions of conventional RISC-system implementations, such as limited available transistor count for on-chip caching, confined data bus width between processor-chip and the off-chip second-level cache, long access times of the second-level cache, strongly limit the achievable performance of the memory hierarchy and may be either removed or at least substantially reduced by the use of 3-D ICs. To evaluate the performance improvements of implementations employing 3-D ICs, a model based on measured miss rates and on an analytical access time model is used. The average time per-instruction is employed as the performance measure. Results of extensive case studies indicate, that substantial performance improvements depending on implementation, cache sizes, cache organization, and miss rates are achievable using 3-D ICs. A comparison of four optimized implementations all with a total cache size of approximately 1 MB yielded performance improvements in the range of 23% to 31% for the implementations employing 3-D-technology over the conventionally implemented system. It is concluded that 3-D-technology will be very attractive for future high performance RISC-systems, since the system performance depends vitally on the performance of the memory hierarchy.

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