The dynamics of latchup turn-on behavior in scaled CMOS
- 1 July 1985
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 32 (7) , 1334-1340
- https://doi.org/10.1109/t-ed.1985.22120
Abstract
This paper presents the dynamics of latchup turn-on behavior in scaled CMOS structures using an exact time-dependent and two-dimensional numerical analysis based on the finite-difference approach. Both the dynamics of surface-induced latchup triggering by a parasitic PMOSFET and direct forward biasing are examined to discuss the two-dimensional effects of parasitic devices in a scaled CMOS structure during latchup turn-on. In the case of an n-well scaled CMOS, the two-dimensional nature of the well structure plays an important role for surface-induced latchup.Keywords
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