Coupling between the front and back interfaces in the gate-controlled P+PN+ diode on silicon-on-insulator
- 30 June 1994
- journal article
- Published by Elsevier in Microelectronics Journal
- Vol. 25 (4) , 307-322
- https://doi.org/10.1016/0026-2692(94)90181-3
Abstract
No abstract availableKeywords
This publication has 8 references indexed in Scilit:
- A self-consistent analytic threshold voltage model for thin SOI n-channel MOSFETsSolid-State Electronics, 1991
- Adaptation of the charge pumping technique to gated p-i-n diodes fabricated on silicon on insulatorIEEE Transactions on Electron Devices, 1991
- Electron trapping in irradiated SIMOX buried oxidesIEEE Electron Device Letters, 1991
- Characterization of hot-electron-stressed MOSFET's by low-temperature measurements of the drain tunnel currentIEEE Transactions on Electron Devices, 1990
- From substrate to VLSI: investigation of hardened SIMOX without epitaxy, for dose, dose rate and SEU phenomenaIEEE Transactions on Nuclear Science, 1988
- Subbreakdown drain leakage current in MOSFETIEEE Electron Device Letters, 1987
- A reliable approach to charge-pumping measurements in MOS transistorsIEEE Transactions on Electron Devices, 1984
- Surface effects on p-n junctions: Characteristics of surface space-charge regions under non-equilibrium conditionsSolid-State Electronics, 1966