LFSROM an algorithm for automatic design synthesis of hardware test pattern generator
- 31 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
The characteristic of the on-chip test pattern generator (TPG) is of prime importance for the overall quality of the test of a circuit with built-in self-test (BIST). The authors describe in this paper a new TPG architecture which is basically composed of a shift register (SR), an OR gate network and a set of multiplexers. It is called a LFSROM and it can be easily designed in a relatively short time for even large test sets. The design synthesis algorithm is described in a step-by-step way by use of a real example so as to show clearly the key parameters to be considered in the design of such an architecture. Furthermore, the silicon area of the LFSROM has been found to be smaller than that of a ROM for the example considered.Keywords
This publication has 6 references indexed in Scilit:
- Test set embedding in a built-in self-test environmentPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- LFSROM: Basic Principle and BIST applicationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- The analysis of one-dimensional linear cellular automata and their aliasing propertiesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1990
- Circuits for pseudoexhaustive test pattern generationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988
- A Class of Test Generators for Built-In TestingIEEE Transactions on Computers, 1983
- Design for Testability—A SurveyIEEE Transactions on Computers, 1982