Optimization of series resistance in sub-0.2 /spl mu/m SOI MOSFET's
- 1 May 1994
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters
- Vol. 15 (5) , 145-147
- https://doi.org/10.1109/55.291591
Abstract
The optimization of device series resistance in ultra-thin film SOI devices is studied through 2-D simulations and process experiments. The series resistance is dependent on the contact resistivity of the silicide to silicon and the silicide geometry. To achieve low series resistance, very thin silicides that do not fully consume the SOI film are needed. A novel cobalt salicidation technology using titanium/cobalt laminates is used to demonstrate sub-0.2 /spl mu/m, thin-film SOI devices with excellent performance and very low device series resistance.Keywords
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