Formalized methodology for data reuse: exploration for low-power hierarchical memory mappings
- 1 December 1998
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- Vol. 6 (4) , 529-537
- https://doi.org/10.1109/92.736124
Abstract
Efficient use of an optimized custom memory hierarchy to exploit temporal locality in the data accesses can have a very large impact on the power consumption in data dominated applications. In the past, experiments have demonstrated that this task is crucial in a complete low-power memory management methodology. But effective formalized techniques to deal with this specific task have not been addressed yet. In this paper, the surprisingly large design freedom available for the basic problem is explored in-depth and the outline of a systematic solution methodology is proposed. The efficiency of the methodology is illustrated on a real-life motion estimation application. The results obtained for this application show power reductions of about 85% for the memory subsystem compared to the case without a custom memory hierarchy. These large gains justify that data reuse and memory hierarchy decisions should be taken early in the design flow.Keywords
This publication has 12 references indexed in Scilit:
- Allocation of multiport memories for hierarchical data streamsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Power exploration for data dominated video applicationsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- An algorithm for array variable clusteringPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Issues in multi-level cache designsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Array placement for storage size reduction in embedded multimedia systemsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Elimination of redundant memory traffic in high-level synthesisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1996
- An analytical model for designing memory hierarchiesIEEE Transactions on Computers, 1996
- Data path synthesisIntegration, 1994
- Performance analysis through memory of a proposed parallel architecture for the efficient use of memory in image processing applicationsPublished by SPIE-Intl Soc Optical Eng ,1991
- Array architectures for block matching algorithmsIEEE Transactions on Circuits and Systems, 1989