Allocation of multiport memories for hierarchical data streams
- 30 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 10 references indexed in Scilit:
- Memory management for high level synthesis applicationsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- The Sprite Input Language-an intermediate format for high level synthesisPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Relative location assignment for repetitive schedulesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Post-processor for data path synthesis using multiport memoriesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- PHIDEO: a silicon compiler for high speed algorithmsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Memory synthesis for high speed DSP applicationsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A new method for the minimization of memory area in high level synthesisPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1991
- Flexible datapath compilation for PhideoPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1991
- Register allocation for design of data format convertersPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1991
- Allocation of multiport memories in data path synthesisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988