Polynomial complexity algorithms for increasing the testability of digital circuits by testing-module insertion

This publication has 14 references indexed in Scilit:

• An incomplete scan design approach to test generation for sequential machines
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
• A dynamic programming approach to the test point insertion problem
  Published by Association for Computing Machinery (ACM) ,1987
• Automatic Design for Testability Via Testability Measures
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1985
• On the Complexity of Estimating the Size of a Test Set
  IEEE Transactions on Computers, 1984
• A Module-Level Testing Approach for Combinational Networks
  IEEE Transactions on Computers, 1976
• Test Point Placement to Simplify Fault Detection
  IEEE Transactions on Computers, 1974
• Fault Folding for Irredundant and Redundant Combinational Circuits
  IEEE Transactions on Computers, 1973
• Fault Detection in Fanout-Free Combinational Networks
  IEEE Transactions on Computers, 1973
• Multiple Fault Detection in Combinational Networks
  IEEE Transactions on Computers, 1972
• Computer Diagnosis Using the Blocking Gate Approach
  IEEE Transactions on Computers, 1971