A 20 ns 64K (4Kx16) NMOS RAM
- 1 October 1984
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 19 (5) , 564-571
- https://doi.org/10.1109/JSSC.1984.1052190
Abstract
A 64K (4K/spl times/16) NMOS RAM is described which uses new circuit techniques and design concepts to achieve an average nominal access time of 20 ns. The RAM was built using a relatively straightforward NMOS technology with single-level metal, single-level polycide, an average minimum feature size of 1.7 /spl mu/m, and an effective channel length of 1.2 /spl mu/m. The chip is organized physically into four 16K blocks. Cell area is 292 /spl mu/m/SUP 2/ with a chip area of 32.6 mm/SUP 2/. A four-device split-wordline cell was used to reduce the wordline delay. Chip organization, simplified clocking and timing, and new circuits were especially important for improved performance. An address buffer with internal reference, a switched decoupled bootstrapped decoder, and a self-timed sense amplifier are described.Keywords
This publication has 8 references indexed in Scilit:
- A 20 ns 64K (4Kx16) NMOS RAMIEEE Journal of Solid-State Circuits, 1984
- Stability and soft error rates of SRAM cellsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1984
- A 25ns 64K SRAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1984
- A 30ns 64K CMOS RAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1984
- A 28ns CMOS SRAM with bipolar sense amplifiersPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1984
- A 20ns 64K CMOS SRAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1984
- A NMOS 64K static RAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1982
- FET logic configurationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1978