A test chip for MOS transistor capacitance characterization
- 19 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
We present test chip for the capacitive characterization of MOS transistors. It allows one to measure accurately capacitances of the transistor and to identify the various components (i.e. gate-source, gate-bulk and gate-drain). From capacitance measurements, it is then possible to determine effective dimensions of the transistor (length and width) as well as gate oxide thickness. As Test Structures enable the measurement of very small capacitances, minimum dimension transistors are studied Author(s) Lorival, R. LIRMM, Univ. des Sci. et Tech. du Languedoc, Montpellier, France Nouet, P.Keywords
This publication has 7 references indexed in Scilit:
- Evaluations of leakage currents and capacitances on elementary CMOS devicesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- New test structures for on-chip absolute and accurate measurement of capacitances in a CMOS processPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- On-chip measurement of interconnect capacitances in a CMOS processPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Direct capacitance measurements of small geometry MOS transistorsMicroelectronics Journal, 1991
- On-chip quasi-static floating-gate capacitance measurement methodPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1990
- A Scaleable Technique for the Measurement of Intrinsic MOS Capacitance with Atto-Farad ResolutionIEEE Journal of Solid-State Circuits, 1985
- A simple method to determine channel widths for conventional and LDD MOSFET'sIEEE Electron Device Letters, 1984