One-shot Reed-Solomon decoding for high-performance dependable systems
- 7 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
This paper presents a scheme of ultra-fast one-shot Reed-Solomon decoding (prototyped (40-34,32,8) soft-IP demonstrating over 7 Gb/s using 0.35 /spl mu/m ASIC technology) and discusses its application to future dependable computer systems, taking a redundant array memory system as an example. We compare different memory configurations and identify improved fault-tolerance to single-bit failures as well as chip and card failures for smaller system overheads when random quad-byte one-shot Reed-Solomon decoding is used. We also discuss an alternative use of the powerful coding gain, i.e., an application to the dynamic refresh interval control of DRAMs, in order to optimize the refresh overheads in performance and power consumption. We believe that the one-shot Reed-Solomon decoding offers an advanced error correction capability for various parts of future high-performance computer systems, where system-level reliability can suffer because of rapidly increasing data size and speed.Keywords
This publication has 17 references indexed in Scilit:
- Single b-bit byte error correcting and double bit error detecting codes for high-speed memory systemsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Symbol error correcting codes for memory applicationsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Durable memory RS/6000 system designPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- G4: a fault-tolerant CMOS mainframePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A new scalable VLSI architecture for Reed-Solomon decodersIEEE Journal of Solid-State Circuits, 1999
- New double-byte error-correcting codes for memory systemsIEEE Transactions on Information Theory, 1998
- An area-efficient VLSI architecture of a Reed-Solomon decoder/encoder for digital VCRsIEEE Transactions on Consumer Electronics, 1997
- Nonbinary double-error-correcting codes designed by means of algebraic varietiesIEEE Transactions on Information Theory, 1995
- Architecture of a high speed Reed-Solomon decoderIEEE Transactions on Consumer Electronics, 1994
- On-the-fly decoder for multiple byte errorsIBM Journal of Research and Development, 1986