A new scalable VLSI architecture for Reed-Solomon decoders
- 1 March 1999
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 34 (3) , 388-396
- https://doi.org/10.1109/4.748191
Abstract
A very-large-scale integration architecture for Reed-Solomon (RS) decoding is presented that is scalable with respect to the throughput rate. This architecture enables given system specifications to be matched efficiently independent of a particular technology. The scalability is achieved by applying a systematic time-sharing technique. Based on this technique, new regular, multiplexed architectures have been derived for solving the key equation and performing finite field divisions. In addition to the flexibility, this approach leads to a small silicon area in comparison with several decoder implementations published in the past. The efficiency of the proposed architecture results from a fine granular pipeline scheme throughout each of the RS decoder components and a small overhead for the control circuitry. Implementation examples show that due to the pipeline strategy, data rates up to 1.28 Gbit/s are reached in a 0.5 μm CMOS technologyKeywords
This publication has 12 references indexed in Scilit:
- A high speed Reed-Solomon codec chip using lookforward architecturePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A 40-MHz encoder-decoder chip generated by a Reed-Solomon code compilerPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A datapath generator for full-custom macros of iterative logic arraysPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A new mapping technique for automated design of highly efficient multiplexed FIR digital filtersPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- An area-efficient VLSI architecture of a Reed-Solomon decoder/encoder for digital VCRsIEEE Transactions on Consumer Electronics, 1997
- New efficient designs for XOR and XNOR functions on the transistor levelIEEE Journal of Solid-State Circuits, 1994
- On computing multiplicative inverses in GF(2/sup m/)IEEE Transactions on Computers, 1993
- Carry-save architectures for high-speed digital signal processingJournal of Signal Processing Systems, 1991
- Reed-Solomon VLSI codec for advanced televisionIEEE Transactions on Circuits and Systems for Video Technology, 1991
- On the VLSI design of a pipeline Reed-Solomon decoder using systolic arraysIEEE Transactions on Computers, 1988