Memory Interference in Synchronous Multiprocessor Systems
- 1 November 1982
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-31 (11) , 1116-1121
- https://doi.org/10.1109/tc.1982.1675928
Abstract
Synchronous N-processor systems with M shared memories are considered. Memory interference is modeled for processor request rates between 0 and 1 per memory cycle. Two probability-based models and one queueing-based model are summarized from prior literature. A new steady-state flow model is introduced. This steady-state model is most accurate overall. The queueing model is somewhat more accurate when request rate is near 1, and M and N are large. Accuracy is established with respect to probabilistic simulation. Additional related models are described.Keywords
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