An 80 ns 32K EEPROM using the FETMOS cell
- 1 October 1982
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 17 (5) , 821-827
- https://doi.org/10.1109/JSSC.1982.1051825
Abstract
A 32K bit EEPROM using the FETMOS (floating-gate electron tunneling MOS) cell has achieved a typical access time of 80 ns and a die size of 20.6 mm/SUP 2/ using approximately 3 /spl mu/m feature sizes. The device has many built-in ease of use and ease of test features, including multimode erase (word, page, and bulk), bulk `O' program, latched inputs for program and erase operation, nonlocked high voltage supply, and margin test capability for both programmed and erased states. A unique TPP (transparent-partial programming) yield enhancement technique, using polysilicon fuse programming, can convert partially good 32K dice into totally good 16K and 8K devices.Keywords
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