Parameterized SPICE subcircuits for multilevel interconnect modeling and simulation
- 1 January 1992
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
- Vol. 39 (11) , 779-789
- https://doi.org/10.1109/82.204126
Abstract
[[abstract]]The authors describe a parameterized interconnect model library generator that provides VLSI designers with a direct link between numerical method-based capacitance simulators and SPICE-like circuit simulators. As a result, interconnect parasitics are parameterized in a manner similar to the parameterization of transistors in SPICE. Therefore, the effort and time needed by circuit designers or EDA tools to prepare distributed multiline R, C SPICE decks for circuit simulations is drastically reduced[[fileno]]2030232010004[[department]]資訊工程學This publication has 13 references indexed in Scilit:
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