Alternating strategies for sequential circuit ATPG
- 23 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 10661409,p. 368-374
- https://doi.org/10.1109/edtc.1996.494327
Abstract
A new sequential circuit test generator, ALT-TEST, is described which alternates repeatedly between two phases of test generation. The first phase uses a simulation-based genetic algorithm, while the second phase uses a deterministic algorithm. The fast execution of the first phase combines with the more powerful test sequence generation and redundancy-identification capabilities of the second phase to produce test sets having high fault coverages in low execution times. The effectiveness of the approach is demonstrated on the ISCAS89 sequential benchmark circuits and several synthesized circuits.Keywords
This publication has 26 references indexed in Scilit:
- A Simulation-Based Test Generation Scheme Using Genetic AlgorithmsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Application of simple genetic algorithms to sequential circuit test generationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- An automatic test pattern generator for large sequential circuits based on Genetic AlgorithmsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1994
- Sequential circuit test generation in a genetic algorithm frameworkPublished by Association for Computing Machinery (ACM) ,1994
- CRIS: A test cultivation program for sequential VLSI circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1992
- Multiple distributions for biased random test patternsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1990
- A directed search method for test generation using a concurrent simulatorIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1989
- Simulator-oriented fault test generatorPublished by Association for Computing Machinery (ACM) ,1988
- Testability-Driven Random Test-Pattern GenerationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
- The Weighted Random Test-Pattern GeneratorIEEE Transactions on Computers, 1975