An automatic test pattern generator for large sequential circuits based on Genetic Algorithms
- 1 January 1994
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 12 references indexed in Scilit:
- Combinational profiles of sequential benchmark circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- CONTEST: a concurrent test generator for sequential circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Application of simple genetic algorithms to sequential circuit test generationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- HITEC: a test generation package for sequential circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Redundancy identification/removal and test generation for sequential circuits using implicit state enumerationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1993
- An efficient algorithm for sequential circuit test generationIEEE Transactions on Computers, 1993
- Sequential test generation based on real-valued logic simulationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1992
- CRIS: A test cultivation program for sequential VLSI circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1992
- PROOFS: a fast, memory-efficient sequential circuit fault simulatorIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1992
- Portable parallel test generation for sequential circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1992