Analysis and design of CMOS Manchester adders with variable carry-skip
- 7 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
A popular VLSI adder implementation is the Manchester adder using dynamic (precharge) logic, where the ripple-carry propagation delay of a block is proportional to the square of its size. The authors examine two different CMOS implementations of the Manchester adder, analyzing them with the RC timing model, which provides a unified way of analyzing both CMOS circuits and interconnect. Based on the RC timing model, they develop efficient (polynomial) algorithms to determine near-optimal, as well as optimal, block sizes for the one-level Manchester adder with variable carry-skip.Keywords
This publication has 8 references indexed in Scilit:
- A Way to Build Efficient Carry-Skip AddersIEEE Transactions on Computers, 1987
- Some optimal schemes for ALU implementation in VLSI technologyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1985
- Signal Delay in RC Tree NetworksIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1983
- PLA versus bit slice: comparison for a 32 bit ALUIEEE Journal of Solid-State Circuits, 1982
- A 32-bit execution unit in an advanced NMOS technologyIEEE Journal of Solid-State Circuits, 1982
- On Determination of Optimal Distributions of Carry Skips in AddersIEEE Transactions on Electronic Computers, 1967
- Skip Techniques for High-Speed Carry-Propagation in Binary Arithmetic UnitsIEEE Transactions on Electronic Computers, 1961
- A parallel arithmetic unit using a saturated-transistor fast-carry circuitProceedings of the IEE Part B: Electronic and Communication Engineering, 1960