Merging multiple FSM controllers for DFT/BIST hardware

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Abstract
Multiple test controllers are often required to control test plans corresponding to various testable design methodologies embedded in a circuit. Implementing these controllers as independent entities adds to the test logic area and may introduce delays on critical control paths of a chip. In this paper we present a technique for combining the test controllers into a minimal area merged controller. This technique consists of sequentially mapping the individual controllers onto the largest one using an A/sup */ algorithm that minimizes the number of implicants in a multiple-valued cover of the merged finite state machine (FSM). We compare this technique with an approach based on controller concatenation and state minimization and show that our technique produces merged machines that, after state and input encoding using the minimum number of bits, have on average 33% and 24% less product terms and area, respectively. For other encoding schemes, our approach results in an average savings of 25% in product terms and area.

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