Reduction of source/drain series resistance and its impact on device performance for PMOS transistors with raised Si/sub 1-x/Gex source/drain
- 1 September 2000
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters
- Vol. 21 (9) , 448-450
- https://doi.org/10.1109/55.863107
Abstract
No abstract availableKeywords
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