SPADES: a simulator for path delay faults in sequential circuits
- 2 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
A fault simulator for path delay faults in synchronous sequential circuits is described, where a test sequence is considered under different combinations of slow and fast clock cycles (clocking schemes). The features of the simulator are: (1) multiple clocking schemes used for the application of a given test sequence are considered in parallel, allowing fast fault simulation for a given sequence, to obtain the highest fault coverage achieveable by every sequence; (2) during the simulation process, it is possible to determine the clocking scheme so as to minimize the number of different clocking schemes to be used with the sequence, without compromising the fault coverage; and (3) a path representation scheme that allows efficient access to path delay faults detected by previous tests is used. Experimental results are presented to demonstrate these features and their effectiveness.Keywords
This publication has 7 references indexed in Scilit:
- Combinational profiles of sequential benchmark circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Delay test generation for synchronous sequential circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Advanced automatic test pattern generation techniques for path delay faultsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- At-speed delay testing of synchronous sequential circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Random pattern testability of delay faultsIEEE Transactions on Computers, 1988
- On Delay Fault Testing in Logic CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
- Modeling and Testing for Timing Faults in Synchronous Sequential CircuitsIEEE Design & Test of Computers, 1984