On the possibility of degradation-free field effect transistors

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Abstract
Time-dependent change in threshold voltage, due to generation of interface/bulk traps, degrades drain current of field effect transistors. In this paper, we show—both theoretically and experimentally—the intriguing possibility of designing degradation-free transistors (with time-invariant drain current), where the degradation in threshold voltage is exactly compensated by improvement in mobility. Such transistors would reduce parametric reliability being a key concern for supply voltage scaling and thereby improve integrated circuit performance by minimizing the guard band voltage used in very large scale integrated circuit design.