Test preparation and fault analysis using a bottom-up methodology

Abstract

The testing methodology for digital VLSI circuits proposed by J.P. Teixeira et al. (1988) is based on the automatic definition of a realistic fault list which depends on the technology, the manufacturing process, and the IC layout. The proposed methodology is extended to include an initial stage of test preparation during the top-down design phase. In this step, an initial test-pattern generation is performed, to be used for test refinement during the bottom-up verification phase. Fault collecting is done by means of a hierarchical layout-to-fault extractor based on the physical failures most likely to occur in MOS designs. Fault list compression is performed, according to user-defined fault listing objectives, by means of a postprocessor. Test vectors derived by means of a gate-level automatic test-pattern generator are validated by using a concurrent switch-level fault simulator. The visualization of undetected faults in the layout is made possible by means of a graphite display facility.

Keywords

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