Optimization of gate oxide N/sub 2/O anneal for CMOSFET's at room and cryogenic temperatures
- 1 January 1994
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 41 (8) , 1364-1372
- https://doi.org/10.1109/16.297731
Abstract
No abstract availableThis publication has 40 references indexed in Scilit:
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