Challenges of a vintage 1994 CMOS logic chip
- 6 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
The viability of projections for a 1994 CMOS logic chip having 3×10 5 transistors/cm 2 , 20-W/cm 2 power dissipation, and 600-MHz clock frequency is assessed with respect to power distribution, signal transmission, and off-chip connections. It is found that current silicon technologies, systematically scaled to 0.25-μm feature size, can achieve complexities of around 2×10 6 transistors/cm 2 , 10-W/cm 2 power dissipation, and 150-MHz clock frequency. Projected functional throughput rates of 5×10 13 -gate Hz/cm 2 are inconsistent with these parameters by more than an order of magnitude. Supplying the chips with power at acceptable Δ I noise will pose the most formidable design challenges Author(s) Hohl, Jakob H. Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA Johnson, B.C.Keywords
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