Probability analysis for CMOS floating gate faults
- 17 December 2002
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 132, 443-448
- https://doi.org/10.1109/edtc.1994.326838
Abstract
No abstract availableThis publication has 18 references indexed in Scilit:
- Test Pattern Generation for Realistic Bridge Faults in CMOS ICsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- A net-oriented method for realistic fault analysisPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Fast multi-layer critical area computationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- IC defect sensitivity for footprint-type spot defectsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1992
- A CMOS fault extractor for inductive fault analysisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988
- VLASIC: A Catastrophic Fault Yield Simulator for Integrated CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1986
- Modeling the critical area in yield forecastsIEEE Journal of Solid-State Circuits, 1985
- Modeling of Lithography Related Yield Losses for CAD of VLSI CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1985
- Modeling of defects in integrated circuit photolithographic patternsIBM Journal of Research and Development, 1984
- Fault Modeling and Logic Simulation of CMOS and MOS Integrated CircuitsBell System Technical Journal, 1978