Submicrometer salicide CMOS devices with self-aligned shallow/deep junctions
- 1 November 1989
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters
- Vol. 10 (11) , 487-489
- https://doi.org/10.1109/55.43112
Abstract
The use of triple-layer oxide/nitride/PETEOS (plasma-enhanced TEOS) gate spacer, CMOS (T-MOS) structure to form shallow/deep junctions with the deep junction self-aligned to the silicide layer on the source/drain area of submicrometer CMOS devices is discussed. Due to the disposable PETEOS spacer layer, only two masks (one for each channel) are needed to form this source/drain junction signature. A T-MOS structure of 0.5- mu m physical gate length has been demonstrated with good device characteristics and ideal junction leakage properties. This T-MOS process, with its moderated doped drain (MDD) structure, is a promising device choice for deep-submicrometer CMOS devices.Keywords
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