Non-robust tests for stuck-fault detection using signal waveform analysis: feasibility and advantages
- 23 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
In this paper we propose to use an output signal waveform analysis method called signal waveform integration for detection of stuck-at failures in combinational circuits. Non-robust tests are applied at-speed or faster to achieve high fault coverage, low test application time and detectability of redundant faults using directed random test generation techniques Author(s) Chatterjee, A. Georgia Inst. of Technol., Atlanta, GA, USA Jayabharathi, R. ; Pant, P. ; Abraham, J.A.Keywords
This publication has 15 references indexed in Scilit:
- Raft: A Novel Program For Rapid-fire Test And Diagnosis Of Digital Logic For Marginal Delays And Delay FaultsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- DELAY TESTING OF DIGITAL CIRCUITS BY OUTPUT WAVEFORM ANALYSISPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Synthesis of delay fault testable combinational logicPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- On the design of robust testable CMOS combinational logic circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- HITEC: a test generation package for sequential circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- CRIS: A test cultivation program for sequential VLSI circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1992
- Probability models for pseudorandom test sequencesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988
- Pseudorandom TestingIEEE Transactions on Computers, 1987
- The Weighted Syndrome Sums Approach to VLSI TestingIEEE Transactions on Computers, 1981
- Diagnosis of Automata Failures: A Calculus and a MethodIBM Journal of Research and Development, 1966