DELAY TESTING OF DIGITAL CIRCUITS BY OUTPUT WAVEFORM ANALYSIS

This publication has 14 references indexed in Scilit:

• On the computation of the ranges of detected delay fault sizes
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
• Delay test generation. I. Concepts and coverage metrics
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
• On the design of robust testable CMOS combinational logic circuits
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
• A variable observation time method for testing delay faults
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• Synthesis and optimization procedures for robustly delay-fault testable combinational logic circuits
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• Gross delay defect evaluation for a CMOS logic design system product
  IBM Journal of Research and Development, 1990
• Quiescent power supply current measurement for CMOS IC defect detection
  IEEE Transactions on Industrial Electronics, 1989
• CrossCheck: a cell based VLSI testability solution
  Published by Association for Computing Machinery (ACM) ,1989
• On Delay Fault Testing in Logic Circuits
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
• An Experimental Delay Test Generator for LSI Logic
  IEEE Transactions on Computers, 1980