On the computation of the ranges of detected delay fault sizes
- 7 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 8 references indexed in Scilit:
- Delay test generation. II. Algebra and algorithmsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- On the detection of delay faultsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Delay test generation. I. Concepts and coverage metricsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Random pattern testability of delay faultsIEEE Transactions on Computers, 1988
- On Delay Fault Testing in Logic CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
- Analysis of Timing Failures Due to Random AC Defects in VLSI ModulesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1985
- Modeling and Testing for Timing Faults in Synchronous Sequential CircuitsIEEE Design & Test of Computers, 1984
- An Experimental Delay Test Generator for LSI LogicIEEE Transactions on Computers, 1980