High-level test generation using physically-induced faults
- 19 November 2002
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableThis publication has 12 references indexed in Scilit:
- Minimal Test Sets for Combinational CircuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Generalization of independent faults for transition faultsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A signal-driven discrete relaxation technique for architectural level test generationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A framework and method for hierarchical test generationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1992
- Hierarchical test generation using precomputed tests for modulesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1990
- Test counting: a tool for VLSI testingIEEE Design & Test of Computers, 1989
- Inductive Fault Analysis of MOS Integrated CircuitsIEEE Design & Test of Computers, 1985
- Error-Correcting Codes for Semiconductor Memory Applications: A State-of-the-Art ReviewIBM Journal of Research and Development, 1984
- Test Generation Algorithms for Computer Hardware Description LanguagesIEEE Transactions on Computers, 1982
- Test Generation for MicroprocessorsIEEE Transactions on Computers, 1980