Bipolar circuit reliability simulation
- 4 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 01631918,p. 181-184
- https://doi.org/10.1109/iedm.1990.237198
Abstract
A model for bipolar hot-carrier degradation has been implemented into the BERT circuit reliability simulator, thus allowing both bipolar and BiCMOS circuit degradation to be simulated. The bipolar module consists of a preprocessor and post-processor for SPICE that require no modification to the SPICE code. Experimental results indicate that the degradation due to alternating reverse-forward stressing representative of BiCMOS gate operation agrees with the Delta I/sub B/ model from DC measurements. The base current degradation for a single device due to electrostatic discharge stress and the offset voltage degradation for an emitter-coupled pair due to DC stress are accurately predicted by the simulator.<>Keywords
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