A high random-access-data-rate 4 Mb DRAM with pipeline operation
- 1 January 1990
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 4 references indexed in Scilit:
- A 22-ns 1-Mbit CMOS high-speed DRAM with address multiplexingIEEE Journal of Solid-State Circuits, 1989
- A new CR-delay circuit technology for high-density and high-speed DRAMsIEEE Journal of Solid-State Circuits, 1989
- A 20-ns 128-kbit*4 high speed DRAM with 330-Mbit/s data rateIEEE Journal of Solid-State Circuits, 1988
- An experimental 1-Mbit BiCMOS DRAMIEEE Journal of Solid-State Circuits, 1987