A 55 ns 16 Mb DRAM
- 13 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 246-247,
- https://doi.org/10.1109/isscc.1989.48275
Abstract
The authors describe a 16-Mb CMOS DRAM (dynamic RAM) with 55-ns access time and 130-mm/sup 2/ chip area. It features a high-speed latched sensing (LS) scheme and a built-in self-test (BIST) function with a microprogrammable ROM in which automatic test pattern generation procedures are stored by microcoded programs. To achieve 55-ns access time, the DRAM combines the LS scheme with conventional double-Al-layer wiring and 5-V peripheral circuits. The bit-line sense circuits, driven at 3.3 V from an internal voltage converter to ensure 0.6 mu m MOS memory cell reliability, are shown. Both sensing speed and signal voltage are lower at 3.3 V operation than at 5 V operation. However, the LS scheme compensates for these drawbacks and achieves fast access time and high sensitivity. Operational waveforms for 55-ns row-address-strobe access time for a typical chip under normal conditions are shown, and chip characteristics are summarized.<>Keywords
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