Progress toward a 30 nm silicon metal–oxide–semiconductor gate technology

We report on progress toward scaling both N-metal–oxide–semiconductor (MOS) and P-metal–oxide–semiconductor MOS transistors to a gate length of 30 nm. We describe lithography and pattern transfer results that are suitable to meet this goal. Scanning capacitance microscopy is used to determine the effective channel lengths and source drain junction depths on cross-sectioned devices to optimize the fabrication process. We present interim electrical results obtained for high performance, down to $L_g\text{=57\hspace{0.05em}}\mathrm{nm},$ N-MOS and P-MOS transistors made using this process. We have also used a device simulation program to predict subthreshold current for N-MOS transistors with gate lengths from 40 to 26 nm. The simulation provides insights into the effects of critical dimension control and edge roughness on leakage current, and has implications for extending large scale integration of MOS technology beyond 50 nm.