Buffered Steiner tree construction with wire sizing for interconnect layout optimization
- 24 December 2002
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 18 references indexed in Scilit:
- New performance driven routing techniques with explicit area/delay tradeoff and simultaneous wire sizingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Simultaneous routing and buffer insertion for high performance interconnectPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A heuristic algorithm for the fanout problemPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Optimal wire sizing and buffer insertion for low power and a generalized delay modelPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A sequential quadratic programming approach to concurrent gate and wire sizingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Optimal wiresizing under Elmore delay modelIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1995
- RC interconnect optimization under the Elmore delay modelPublished by Association for Computing Machinery (ACM) ,1994
- Performance-driven interconnect design based on distributed RC delay modelPublished by Association for Computing Machinery (ACM) ,1993
- The rectilinear steiner arborescence problemAlgorithmica, 1992
- Signal Delay in RC Tree NetworksIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1983