A novel 6H-SiC power DMOSFET with implanted p-well spacer
- 1 July 1999
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters
- Vol. 20 (7) , 354-356
- https://doi.org/10.1109/55.772374
Abstract
In this letter, we utilize a lower thermal budget with an aluminum doped p-well to minimize the effect of "step bunching" and a new structural design with deep spacer implants to prevent the JFET "pinching" action at small p-well spacings (5 /spl mu/m) in planar vertical double implanted MOSFET (DIMOS) devices fabricated on 6H-SiC. A specific ON-resistance of 42 m/spl Omega/-cm/sup 2/ (further reducible by 35% through simple design modification), which represents a 100% reduction over devices which did not receive the spacer implants, is observed on the 2-/spl mu/m channel devices. This novel scheme will allow increased packing densities for high power applications using the DIMOS structure in SiC.Keywords
This publication has 10 references indexed in Scilit:
- High-voltage accumulation-layer UMOSFET's in 4H-SiCIEEE Electron Device Letters, 1998
- On the correlation between the carbon content and the electrical quality of thermally grown oxides on p-type 6H–Silicon carbideApplied Physics Letters, 1998
- 2.6 kV 4H-SiC lateral DMOSFETsIEEE Electron Device Letters, 1998
- The planar 6H-SiC ACCUFET: a new high-voltage power MOSFET structureIEEE Electron Device Letters, 1997
- SiC Integrated MOSFETsPhysica Status Solidi (a), 1997
- Thin oxide growth on 6H-silicon carbideMicroelectronic Engineering, 1997
- High-voltage double-implanted power MOSFET's in 6H-SiCIEEE Electron Device Letters, 1997
- Aluminum and boron ion implantations into 6H-SiC epilayersJournal of Electronic Materials, 1996
- Improved oxidation procedures for reduced SiO2/SiC defectsJournal of Electronic Materials, 1996
- Surface morphology of silicon carbide epitaxial filmsJournal of Electronic Materials, 1995