A CMOS quaternary threshold logic full adder circuit with transparent latch
- 4 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
A circuit that realizes the quaternary threshold logic full adder function with transparent latching has been realized in a standard polysilicon-gate CMOS technology. In its FOLLOW mode, the quaternary full adder accepts two quaternary inputs and a binary CARRY input, and develops a two-quaternary-digit output word that is the base-four sum of the inputs. In the HOLD mode, these output states are held by the transparent multiple-valued latch subcircuit. The circuit is presented and its experimental performance described.Keywords
This publication has 10 references indexed in Scilit:
- Neural networks using analog multipliersPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- CMOS quaternary latchElectronics Letters, 1989
- Design of parallel hardware neural network systems from custom analog VLSI 'building block' chipsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1989
- A general purpose analog neural computerPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1989
- A 32*32-bit multiplier using multiple-valued MOS current-mode circuitsIEEE Journal of Solid-State Circuits, 1988
- Quaternary threshold logic full-adder circuit with complementary inputs†International Journal of Electronics, 1984
- CMOS current comparator circuitElectronics Letters, 1983
- Multivalued Integrated Injection LogicIEEE Transactions on Computers, 1977
- Realization of a multivalued integrated injection logic (MI/sup 2/L) full adderIEEE Journal of Solid-State Circuits, 1977
- Threshold I/sup 2/L and its applications to binary symmetric functions and multivalued logicIEEE Journal of Solid-State Circuits, 1977