Electrical properties of Ge-implanted and oxidized Si

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Abstract
Metal-oxide semiconductor (MOS) structures fabricated on high dose Ge-implanted Si by thermal oxidation have been studied. From the analysis of capacitance-voltage (C-V) characteristics, the electrical properties of the interface between oxide and Si substrate were found to be greatly modified by a SiGe layer which forms by segregation of Ge during oxidation. The C-V curves are consistent with a model incorporating a narrower band gap than that of Si close to the interface. An electronic band model which includes a Si/SiGe heterojunction under the grown oxide is therefore used to interpret the experimental results. For n-type samples the C-V curves are analysed in terms of interface trap states. Variations in the density of interface states with the Ge implantation dose are examined. The effects of different oxidation conditions and N2 annealing on the C-V characteristics and trap density of the n-type samples are studied.
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