An analytical CMOS inverter delay model including channel-length modulations
- 1 January 1992
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 27 (9) , 1303-1306
- https://doi.org/10.1109/4.149422
Abstract
An analytical delay model of a CMOS inverter that includes channel-length modulation and source-drain resistance as well as high-field effects is introduced. This model is based on the improved short-channel MOSFET model derived from a quasi-two-dimensional analysis of operation in the saturation region. Calculations of the rise, fall, and delay times show good agreement with SPICE MOS level three simulationsKeywords
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