Power Efficiency for Variation-Tolerant Multicore Processors
- 1 October 2006
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 304-309
- https://doi.org/10.1109/lpe.2006.4271854
Abstract
No abstract availableThis publication has 19 references indexed in Scilit:
- Mitigating Amdahl's Law through EPI ThrottlingACM SIGARCH Computer Architecture News, 2005
- Razor: a low-power pipeline based on circuit-level timing speculationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2004
- Parameter variations and impact on circuits and microarchitecturePublished by Association for Computing Machinery (ACM) ,2003
- Effectiveness of adaptive supply voltage and body bias for reducing impact of parameter variations in low power and high performance microprocessorsIEEE Journal of Solid-State Circuits, 2003
- Processor Power Reduction Via Single-ISA Heterogeneous Multi-Core ArchitecturesIEEE Computer Architecture Letters, 2003
- The SPLASH-2 programs: characterization and methodological considerationsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Automatically characterizing large scale program behaviorPublished by Association for Computing Machinery (ACM) ,2002
- SPEC CPU2000: measuring CPU performance in the New MillenniumComputer, 2000
- Power-aware microarchitecture: design and modeling challenges for next-generation microprocessorsIEEE Micro, 2000
- Environment for PowerPC microarchitecture explorationIEEE Micro, 1999