A Practical Approach to Fault Simulation and Test Generation for Bridging Faults

1 July 1985

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers

Vol. C-34 (7) , 658-663
https://doi.org/10.1109/tc.1985.1676604

Abstract

In this correspondence we prepent a practical approach to fault simulation and test generation for bridging faults in combinational circuits. Unlike previous work, we consider Unrestricted bridging faults, including those that introduce feedback. Our approach is based on extending fault simulation and test generation for stuck faults to cover bridging faults as well. We consider combinational testing only, and show that adequate bridging fault coverage can be obtained in most cases without using sequences of vectors.

Keywords

This publication has 9 references indexed in Scilit:

Critical Path Tracing: An Alternative to Fault Simulation
IEEE Design & Test of Computers, 1984
Detection and Location of Input and Feedback Bridging Faults Among Input and Output Lines
IEEE Transactions on Computers, 1980
Undetectability of Bridging Faults and Validity of Stuck-At Fault Test Sets
IEEE Transactions on Computers, 1980
Optimal Detection of Bridge Faults and Stuck-At Faults in Two-Level Logic
IEEE Transactions on Computers, 1978
Diagnosis of Short-Circuit Faults in Combinational Circuits
IEEE Transactions on Computers, 1974
Bridging and Stuck-At Faults
IEEE Transactions on Computers, 1974
Concurrent simulation of nearly identical digital networks
Computer, 1974
Enhancing Testability of Large-Scale Integrated Circuits via Test Points and Additional Logic
IEEE Transactions on Computers, 1973
A Deductive Method for Simulating Faults in Logic Circuits
IEEE Transactions on Computers, 1972