Formal verification by symbolic evaluation of partially-ordered trajectories
- 1 March 1995
- journal article
- research article
- Published by Springer Nature in Formal Methods in System Design
- Vol. 6 (2) , 147-189
- https://doi.org/10.1007/bf01383966
Abstract
No abstract availableKeywords
This publication has 26 references indexed in Scilit:
- Model checking and abstractionPublished by Association for Computing Machinery (ACM) ,1992
- A methodology for hardware verification based on logic simulationJournal of the ACM, 1991
- On the complexity of VLSI implementations and graph representations of Boolean functions with application to integer multiplicationIEEE Transactions on Computers, 1991
- Formal verification of memory circuits by switch-level simulationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1991
- Fast Methods for Switch-Level Verification of MOS CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
- Boolean Analysis of MOS CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
- Graph-Based Algorithms for Boolean Function ManipulationIEEE Transactions on Computers, 1986
- Automatic verification of finite-state concurrent systems using temporal logic specificationsACM Transactions on Programming Languages and Systems, 1986
- On a Ternary Model of Gate NetworksIEEE Transactions on Computers, 1979
- Edinburgh LCFLecture Notes in Computer Science, 1979