Recursive equations for hardwired binary adders

Publisher Website
Google Scholar
Abstract
A sum equation for the implementation of parallel hardwired binary adders is introduced. It is suggested that the proposed sum equation, when compared with Ling's high-speed sum, will result in some advantages, and that it can be used in the design of high-speed parallel adders using generally available technologies. It is shown that a 32-bit adder can be designed in three stages using 3 × 8 AND-ORs, 3 × 4 AND-OR-INVERTs and 2 × 4 OR-ANDs CMOS gates, and that a bipolar adder can be designed in four stages, with three-way NANDs and eight-way AND-dotting. In addition, it is suggested that a three-stage 32-bit adder using NANDs and AND-dotting is most likely unrealistic. The paper also describes the design of a number of adders, and discusses the speed, feasibility and complexity of their design.

This publication has 6 references indexed in Scilit: