Row/Column Replacement for the Control of Hard Defects in Semiconductor RAM's
- 1 November 1986
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-35 (11) , 996-1000
- https://doi.org/10.1109/tc.1986.1676701
Abstract
We describe and analyze row/column replacement, the technique currently used to control hard cell defects in semiconductor RAM's during manufacture. This strategy is shown to be asymptotically ineffective; it is demonstrated that this ineffectiveness may become a limiting issue for very large memory arrays.Keywords
This publication has 11 references indexed in Scilit:
- A submicron 1 Mbit dynamic RAM with a 4-bit-at-a-time built-in ECC circuitIEEE Journal of Solid-State Circuits, 1984
- Sources of failures and yield improvement for VLSI and restructurable interconnects for RVLSI and WSI: Part I—Sources of failures and yield improvement for VLSIProceedings of the IEEE, 1984
- Circuit techniques for a VLSI memoryIEEE Journal of Solid-State Circuits, 1983
- Error-correction technique for random-access memoriesIEEE Journal of Solid-State Circuits, 1982
- A redundancy circuit for a fault-tolerant 256K MOS RAMIEEE Journal of Solid-State Circuits, 1982
- Laser programmable redundancy and yield improvement in a 64K DRAMIEEE Journal of Solid-State Circuits, 1981
- Yield Model for Productivity Optimization of VLSI Memory Chips with Redundancy and Partially Good ProductIBM Journal of Research and Development, 1980
- A fault-tolerant 64K dynamic random-access memoryIEEE Transactions on Electron Devices, 1979
- Alpha-particle-induced soft errors in dynamic memoriesIEEE Transactions on Electron Devices, 1979
- Multiple word/bit line redundancy for semiconductor memoriesIEEE Journal of Solid-State Circuits, 1978