Development of a fault model and test algorithms for embedded DRAMs
- 30 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 815-824
- https://doi.org/10.1109/test.1993.470620
Abstract
Embedded DRAMs are an integral part of modern ICs. Owing to limited accessibility, the testing of embedded memories is a time consuming exercise. Such memories designed in a standard VLSI process show susceptibility to catastrophic as well as non-catastrophic defects. Taking into account catastrophic and non-catastrophic defects, an accurate and efficient fault model has been developed. Using this fault model linear test algorithms of complexity 8N and 9N have been developed Author(s) Sachdev, M. Philips Res. Lab., Eindhoven, Netherlands Verstraelen, M.Keywords
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