Defect tolerance on the Teramac custom computer
- 23 November 2002
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 116-123
- https://doi.org/10.1109/fpga.1997.624611
Abstract
No abstract availableThis publication has 14 references indexed in Scilit:
- Fault spectrum analysis for fast spare allocation in reconfigurable arraysPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Lessons learnt from designing a wafer scale 2D arrayPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Making defect avoidance nearly invisible to the user in wafer scale field programmable gate arraysPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Defect tolerant SRAM based FPGAsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Fast search algorithms for reconfiguration problemsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Utilizing spares in multichip modules for the dual function of fault coverage and fault diagnosisPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- ADTS: an array defect-tolerance scheme for wafer scale gate arraysPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Totally defect-tolerant arrays capable of quick broadcastingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- General-purpose systolic arraysComputer, 1993
- On a Pin Versus Block Relationship For Partitions of Logic GraphsIEEE Transactions on Computers, 1971