Modeling and analysis of manufacturing variations

This publication has 7 references indexed in Scilit:

• A statistical critical dimension control at CMOS cell level
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• Within-chip variability analysis
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1997
• A gate-delay model for high-speed CMOS circuits
  Published by Association for Computing Machinery (ACM) ,1994
• Relating statistical MOSFET model parameter variabilities to IC manufacturing process fluctuations enabling realistic worst case design
  IEEE Transactions on Semiconductor Manufacturing, 1994
• Realistic statistical worst-case simulations of VLSI circuits
  IEEE Transactions on Semiconductor Manufacturing, 1991
• A Critical Path Delay Check System
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,1981