Dual-regulator dual-decoding-trimmer DRAM voltage limiter for burn-in test

This publication has 10 references indexed in Scilit:

• A tunable CMOS-DRAM voltage limiter with stabilized feedback amplifier
  IEEE Journal of Solid-State Circuits, 1990
• A 45-ns 16-Mbit DRAM with triple-well structure
  IEEE Journal of Solid-State Circuits, 1989
• An experimental 16-Mbit DRAM with reduced peak-current noise
  IEEE Journal of Solid-State Circuits, 1989
• A 1-Mbit BiCMOS DRAM using temperature-compensation circuit techniques
  IEEE Journal of Solid-State Circuits, 1989
• Dual-operating-voltage scheme for a single 5-V 16-Mbit DRAM
  IEEE Journal of Solid-State Circuits, 1988
• A 65-ns 4-Mbit CMOS DRAM with a twisted driveline sense amplifier
  IEEE Journal of Solid-State Circuits, 1987
• A new on-chip converter for submicrometer high-density DRAMs
  IEEE Journal of Solid-State Circuits, 1987
• A 4-Mbit DRAM with half-internal-voltage bit-line precharge
  IEEE Journal of Solid-State Circuits, 1986
• An experimental 1Mb DRAM with on-chip voltage limiter
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,1984
• A new NMOS temperature-stable voltage reference
  IEEE Journal of Solid-State Circuits, 1978